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verilog恒系数乘法器
- verilog恒系数乘法器
fpga实现乘法器
- 用verilog语言实现的乘法器,可以实现正负数的乘法。
实用verilog代码(乘法器,触发器,FIFO等)
- 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
costas的verilog程序
- costas的verilog程序,包含乘法器,DDS,鉴相器,环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘,采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
verilog-example
- 4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器-failed to translate
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
8bit_mult
- 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
BBooth
- 基verilog 布斯乘法器 4位位宽,本人不才,仅做参考-Booth multiplier based verilog
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作,又可完成子字并行操作模式,即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
mltiply_machine
- verilog语言写的乘法器,每一步经过验证,毫发无损,拿出来与大家共享,在quartus II 上编程,仿真在cyclone 2上!!谢谢!-written multiplier verilog language, every step of the proven, intact, and show to share the quartus II on programming, simulation in cyclone 2 on! ! Thank you!
16 bit signed number multiplier
- 16位有符号数乘法器,使用Booth编码和华莱士树,提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码,两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
multiplier
- Booth乘法器是属于位操作乘法器,采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)